1. Field of the Invention
Embodiments of the invention relate to switching power supply devices that receive a rectified AC voltage and deliver a stable DC voltage.
2. Description of the Related Art
A power factor correction (PFC) converter of a step-up chopper type, a type of switching power supply device, generates a stable DC output voltage while generating an input current proportional to an input voltage utilizing self-excited oscillation of an inductor. The PFC converter has excellent characteristics including small-size, high efficiency, and production at a low cost. FIG. 4 shows a schematic construction of this type of switching power supply device, which is a power factor correction converter, in which the reference symbol BD designates a rectifier circuit that rectifies an AC power given from an AC power supply through an input filter F and delivers the rectified voltage to the switching power supply device.
This switching power supply device is provided with an inductor L connected to the rectifier circuit BD and a switching element Q that forms a current path from the rectifier circuit BD through the inductor L in the ON state of the switching element Q. The switching power supply device is further provided with a diode D that forms a current path between the inductor L and an output capacitor C2 in the OFF state of the switching element Q and a control circuit CONT that ON/OFF drives the switching element Q to control the current flowing through the inductor L. The symbol C1 designates an input capacitor.
The switching element Q provides the inductor L with a current proportional to the input voltage applied to the switching power supply device in the ON state of the switching element Q. The current flowing through the inductor L, inductor current, rises from zero over the ON period of the switching element Q. Upon turning OFF of the switching element Q, the voltage across the inductor L changes its polarity and the inductor current is delivered to the output capacitor C2 in the output side through the diode D. When the inductor current flowing out from the inductor L becomes zero, the switching element Q is turned ON again to transfer to the next operation cycle. This procedure is repeated. Japanese Unexamined Patent Application Publication No. 2010-220330 (also referred to herein as “Patent Document 1”) and Japanese Unexamined Patent Application Publication No. 2011-103737 (also referred to herein as “Patent Document 2”) disclose this kind of procedure.
The control circuit CONT for conducting the ON/OFF control of the switching element Q is a power supply driving IC to drive directly a MOS-FET used for the switching element Q. The control circuit CONT comprises an error detector 11 for detecting an error Comp (comparison reference voltage) that is a difference between an output voltage Vo detected by division with series-connected resistors R1 and R2, and a preset target output voltage. An ON width generating circuit 12 indicated in FIG. 4 generates a signal ‘OFF’ that determines an ON width Ton of the switching element Q, which is a MOS-FET, based on the error Comp detected by the error detector 11 and delivers the signal ‘OFF’ to a flip-flop 13 to reset the flip-flop.
The flip-flop 13 is set to make the output q thereof High and reset to make the output q Low. Receiving the output q from the flip-flop 13, a driving circuit 14 ON/OFF drives the switching element Q. Thus, the ON width generating circuit 12 resets the flip-flop 13 with the output signal ‘OFF’ to turn OFF the switching element Q.
The control circuit CONT comprises a zero current detecting circuit 15 that detects an inductor current Ir from a negative voltage developing across a resistor R3 inserted in a current path including the inductor L in particular in a power supply line at the negative side. The zero current detecting circuit 15 compares a voltage Vcs developing across the resistor R3 in proportion to the inductor current Ir with a preset reference voltage Vref, and delivers a zero current detecting signal Vzcd when the inductor current Ir reaches the zero level. The reference voltage Vref is set at as nearly to 0 mV as possible, but generally in the range of −10 mV to −5 mV in view of power supply noise and circuit parameter variation.
In order to turn ON the switching element Q at the timing of the lowest voltage, a valley of voltage, undergone by the switching element Q, the zero current detecting signal Vzcd delivered by the zero current detecting circuit 15 is delayed by a certain period of time Td in a delay circuit 16 and then given to the flip-flop 13 to set the flip-flop 13. Thus, the zero current detecting circuit 15 sets the flip-flop 13 with the zero current detecting signal Vzcd and turns ON the switching element Q.
The delay of the zero current detecting signal Vzcd in the delay circuit 16 is briefly described below. In the OFF state of the switching element Q, the switching element Q undergoes a high voltage developed at the inductor L, and the inductor current Ir decreases caused by flowing out of the current from the inductor L. When the inductor current Ir returns to the zero level, a critical point, the zero current detecting circuit 15 detects the zero level and delivers the zero current detecting signal Vzcd. The inductor current, however, swings further down to negative side due to resonant oscillation created by the inductance of the inductor L and a parasitic capacitance component in the circuit of the current path including the inductor L. The resonant oscillation also causes oscillation in the voltage undergone by the switching element Q. The voltage on the switching element Q is the lowest, a valley of voltage oscillation, at the moment when the inductor current Ir changes from a negative value to a positive value.
The delay circuit 16 delays the zero current detecting signal Vzcd after the zero current detection so as to turn ON the switching element Q at the timing of the lowest voltage, at a valley of the voltage resonant oscillation, undergone by the switching element Q. The delay time Td of the delay circuit 16 is fixedly set in general corresponding to the circuit parameters of the switching power supply device 1. Owing to the delay of the zero current detecting signal Vzcd performed in the delay circuit 16, switching loss on turning ON of the switching element Q is limited to the smallest and the surge current on turning ON of the switching element Q is also limited to the smallest.
The inductor current Ir varies with time corresponding to ON/OFF operation of the switching element Q. The rate of the variation, the gradient, depends on the input voltage Vi, the output voltage Vo, and the inductance of the inductor L, and other parameters in the circuit. The variation of the inductor current Ir also changes a rate of variation, a gradient, of the voltage Vcs, which is proportional to the inductor current Ir. As a result, even though the zero current detecting signal Vzcd is generated based on the comparison between the voltage Vcs and the reference voltage Vref, a discrepancy time Tzcd occurs, as shown in FIG. 5, between the timing at critical point arrival at which the inductor current Ir actually returns to zero from a negative value and the timing of the lowest voltage, the valley of voltage oscillation, on the switching element Q.
Because the inductor current Ir varies relating to an instantaneous value of the input voltage Vi varying with the phase as shown in FIG. 6, the discrepancy time Tzcd also varies with the input voltage Vi. At a specific example of phase A with a low input voltage Vi, the gradient of the voltage Vcs is large to make the discrepancy time Tzcd small. In contrast, at the phase D with a high input voltage Vi, the gradient of the voltage Vcs is small making the discrepancy time Tzcd large.
Despite this circumstance, the delay time Td is fixedly set in the delay circuit 16. As a consequence, at a phase of high input voltage Vi, for example, the switching element Q operates in a continuous mode. Further, even if the delay time Td for the zero current detecting signal Vzcd is adjusted so that the switching element Q is turned ON at the timing of the lowest voltage on the switching element Q, the switching element Q is turned ON at a timing earlier or later than the valley of voltage oscillation due to variation of the discrepancy time Tzcd. Therefore, the switching efficiency deteriorates and the power factor decreases. Thus, there exist certain shortcomings in the related art.